module eightOut(clk, rst, o1, o2, o3, o4, o5, o6, o7, o8, aE, enable, position, in);

input clk;// (Key 3)
input rst;// (SW 17)

input [3:0]position;// position of each display signal, made up of three switches(SW 14, SW 13, SW12---->0..0..0)
input enable;// enable for each position(SW15)
input aE;// enabler for the algorithim (SW 16)
input [3:0]in;// value assigned to each position

output [6:0]o1;// outputs for HEX display(HEX 0)
output [6:0]o2;//(HEX 1)
output [6:0]o3;//(HEX 2)
output [6:0]o4;//(HEX 3)
output [6:0]o5;//(HEX 4)
output [6:0]o6;//(HEX 5)
output [6:0]o7;//(HEX 6)
output [6:0]o8;//(HEX 7)

//HEX display for algorithm
reg [6:0]o1;
reg [6:0]o2;
reg [6:0]o3;
reg [6:0]o4;
reg [6:0]o5;
reg [6:0]o6;
reg [6:0]o7;
reg [6:0]o8;

reg [4:0] state;
reg [4:0] nextState;

//states
parameter start  = 5'd0;
parameter a_b = 5'd1;
parameter b_c = 5'd2;
parameter c_d = 5'd3;
parameter d_e = 5'd4;
parameter e_f = 5'd5;
parameter f_g = 5'd6;
parameter g_h = 5'd7;
parameter h_i = 5'd8;
parameter i_j = 5'd9;
parameter j_k = 5'd10;
parameter k_l = 5'd11;
parameter l_m = 5'd12;
parameter m_n = 5'd13;
parameter n_o = 5'd14;
parameter o_p = 5'd15;
parameter finish = 5'd16;
parameter endTime = 5'd17;

reg [2:0] countAlg;// counter used for finished state

reg [3:0] outA;// number outputs used for algorithim
reg [3:0] outB;
reg [3:0] outC;
reg [3:0] outD;
reg [3:0] outE;
reg [3:0] outF;
reg [3:0] outG;
reg [3:0] outH;
reg [3:0] outI;
reg [3:0] outJ;
reg [3:0] outK;
reg [3:0] outL;
reg [3:0] outM;
reg [3:0] outN;
reg [3:0] outO;
reg [3:0] outP;

reg [3:0]out1;// register outputs used for initializing input values 
reg [3:0]out2;
reg [3:0]out3;
reg [3:0]out4;
reg [3:0]out5;
reg [3:0]out6;
reg [3:0]out7;
reg [3:0]out8;
reg [3:0]out9;
reg [3:0]out10;
reg [3:0]out11;
reg [3:0]out12;
reg [3:0]out13;
reg [3:0]out14;
reg [3:0]out15;
reg [3:0]out16;

reg [5:0]count; // counter used for seconds
reg [31:0]timer;// current clock time
reg [31:0]timerMax;// maxed timer input

//display manual inputs to HEX
always @ (posedge clk)
begin 
	if (rst == 1'b1)
		begin 
			out1 <= 4'd0;
			out2 <= 4'd0;
			out3 <= 4'd0;
			out4 <= 4'd0;
			out5 <= 4'd0;
			out6 <= 4'd0;
			out7 <= 4'd0;
			out8 <= 4'd0;
			out9 <= 4'd0;
			out10 <= 4'd0;
			out11 <= 4'd0;
			out12 <= 4'd0;
			out13 <= 4'd0;
			out14 <= 4'd0;
			out15 <= 4'd0;
			out16 <= 4'd0;
		end
	else 
		begin
			case (position)
				    4'd0: begin
							    if (enable == 1'b1)
									begin
										out1 <= in;
									end
								else
									begin
										out1 <= out1;
									end
							  end
								
					  4'd1: begin
								  if (enable == 1'b1)
								     begin
										  out2 <= in;
									  end
								  else
									  begin
										  out2 <= out2;
									  end
							  end
							
						4'd2: begin
									if (enable == 1'b1)
										begin
											out3 <= in;
										end
									else
										begin
											out3 <= out3;
										end
									end
						4'd3:  begin
									if (enable == 1'b1)
										begin
											out4 <= in;
										end
									else
										begin
											out4 <= out4;
										end
									end
									
						4'd4:  begin
									if (enable == 1'b1)
										begin
											out5 <= in;
										end
									else
										begin
											out5 <= out5;
										end
									end
						4'd5:  begin
									if (enable == 1'b1)
										begin
											out6 <= in;
										end
									else
										begin
											out6 <= out6;
										end
									end			
						4'd6:  begin
									if (enable == 1'b1)
										begin
											out7 <= in;
										end
									else
										begin
											out7 <= out7;
										end
									end			
						4'd7:  begin
									if (enable == 1'b1)
										begin
											out8 <= in;
										end
									else
										begin
											out8 <= out8;
										end
									end		
						4'd8:  begin
									if (enable == 1'b1)
										begin
											out9 <= in;
										end
									else
										begin
											out9 <= out9;
										end
									end			
						4'd9:  begin
									if (enable == 1'b1)
										begin
											out10 <= in;
										end
									else
										begin
											out10 <= out10;
										end
									end			
									
						4'd10:  begin
									if (enable == 1'b1)
										begin
											out11 <= in;
										end
									else
										begin
											out11 <= out11;
										end
									end			
									
						4'd11:  begin
									if (enable == 1'b1)
										begin
											out12 <= in;
										end
									else
										begin
											out12 <= out12;
										end
									end			
									
						4'd12:  begin
									if (enable == 1'b1)
										begin
											out13 <= in;
										end
									else
										begin
											out13 <= out13;
										end
									end			
									
						4'd13:  begin
									if (enable == 1'b1)
										begin
											out14 <= in;
										end
									else
										begin
											out14 <= out14;
										end
									end			
									
						4'd14:  begin
									if (enable == 1'b1)
										begin
											out15 <= in;
										end
									else
										begin
											out15 <= out15;
										end
									end			
									
						4'd15:  begin
									if (enable == 1'b1)
										begin
											out16 <= in;
										end
									else
										begin
											out16 <= out16;
										end
									end							
						endcase
					end
				end
						
						

// update next state
always @ (posedge clk) 
	begin
	timerMax = 32'd5000000;  
		if (rst == 1'b1)				 
			begin 
				timer <= 1'b0;
				count <= 1'b0;
				state <= start;// resets state
			end
		else 
			begin 
				timer = timer + 1'b1;// adds one value to the timer for each clock cycle
				if ( timer == timerMax)// determines if the timer has gone through [5*(10^7)] cycles
					begin// state update within timer always
						if (rst == 1'b1)
							begin
								if (aE == 1'b1)// enable signal must be within the state update to mandate algorithim use
									begin
										state <= start;
									end
								else
									begin
										state <= state;
									end
							end
						else
							begin
								if (aE == 1'b1)
									begin
										state <= nextState;
										count <= count + 1'b1;// after one second, the counter is raised by one
									end
								else
									begin
										state <= state;
									end
								
								timer <= 1'b0;
							end
					end
				else 
					begin 
						count <= count;
					end 
			end
	end
//calculate nextState
always @ (*)
	begin
 
		case(state)
	 
			start:begin
							nextState = a_b;
					end
			 
			a_b:	begin
							nextState = b_c;
					end

				
			b_c:	begin
							nextState = c_d;
					end
				
			c_d:	begin
						nextState = d_e;
					end
					
			d_e:	begin
						nextState = e_f;
					end	
				
			e_f:	begin
						nextState = f_g;
					end	
					
			f_g:	begin
						nextState = g_h;
					end
					
			g_h:	begin
						nextState = h_i;
					end
					
			h_i:	begin
						nextState = i_j;
					end	
			
			i_j:  begin 
						nextState = j_k;
					end
					
			j_k:	begin
						nextState = k_l;
					end	
					
			k_l:	begin
						nextState = l_m;
					end	
					
			l_m:	begin
						nextState = m_n;
					end	
					
			m_n:	begin
						nextState = n_o;
					end	
					
			n_o:	begin
						nextState = o_p;
					end		
					
			o_p:	begin
						nextState = finish;
					end	
					
			finish:	begin
							countAlg = countAlg + 1'b1;
								if(countAlg < 4'd10)
									begin
										nextState = a_b;
									end
								else
									begin
										nextState = endTime;
									end								
						end
			
			endcase		
	end

// state logic
always @ (posedge clk)
	begin
		case(state)
			start: begin
					outA <= out1;
					outB <= out2;
					outC <= out3;
					outD <= out4;
					outE <= out5;
					outF <= out6;
					outG <= out7;
					outH <= out8;
					outI <= out9;
					outJ <= out10;
					outK <= out11;
					outL <= out12;
					outM <= out13;
					outN <= out14;
					outO <= out15;
					outP <= out16;
			end
			
			a_b:	begin
					if(outA < outB)
					begin
						outA <= outB;
						outB <= outA;
					end
				else
				begin
					outA <= outA;
					outB <= outB;
				end
			end

			b_c:  begin
						if(outB < outC)
							begin
								outB <= outC;
								outC <= outB;
							end
						else
							begin
								outB <= outB;
								outC <= outC;
							end
					end

			c_d: begin
					if(outC < outD)
						begin
							outC <= outD;
							outD <= outC;
						end
					else
						begin
							outC <= outC;
							outD <= outD;
						end
					end
			
			d_e: begin
					if(outD < outE)
						begin
							outD <= outE;
							outE <= outD;
						end
					else
						begin
							outD <= outD;
							outE <= outE;
						end
					end
					
			e_f: begin
					if(outE < outF)
						begin
							outE <= outF;
							outF <= outE;
						end
					else
						begin
							outE <= outE;
							outF <= outF;
						end
					end		
					
			f_g: begin
					if(outF < outG)
						begin
							outF <= outG;
							outG <= outF;
						end
					else
						begin
							outG <= outG;
							outF <= outF;
						end
					end		
			g_h: begin
					if(outG < outH)
						begin
							outG <= outH;
							outH <= outG;
						end
					else
						begin
							outG <= outG;
							outH <= outH;
						end
					end
					
			h_i: begin
					if(outH < outI)
						begin
							outH <= outI;
							outI <= outH;
						end
					else
						begin
							outI <= outI;
							outH <= outH;
						end
					end
					
			i_j: begin
					if(outI < outJ)
						begin
							outI <= outJ;
							outJ <= outI;
						end
					else
						begin
							outI <= outI;
							outJ <= outJ;
						end
					end	
					
			j_k: begin
					if(outJ < outK)
						begin
							outJ <= outK;
							outK <= outJ;
						end
					else
						begin
							outK <= outK;
							outJ <= outJ;
						end
					end
					
			k_l: begin
					if(outK < outL)
						begin
							outK <= outL;
							outL <= outK;
						end
					else
						begin
							outK <= outK;
							outL <= outL;
						end
					end		
					
			l_m: begin
					if(outL < outM)
						begin
							outL <= outM;
							outM <= outL;
						end
					else
						begin
							outL <= outL;
							outM <= outM;
						end
					end		
					
			m_n: begin
					if(outM < outN)
						begin
							outM <= outN;
							outN <= outM;
						end
					else
						begin
							outM <= outM;
							outN <= outN;
						end
					end	
					
			n_o: begin
					if(outN < outO)
						begin
							outN <= outO;
							outO <= outN;
						end
					else
						begin
							outN <= outN;
							outO <= outO;
						end
					end	
					
			o_p: begin
					if(outO < outP)
						begin
							outO <= outP;
							outP <= outO;
						end
					else
						begin
							outO <= outO;
							outP <= outP;
						end
					end	
					
			endTime: begin
				count <= count;
						end
			endcase
	end

	//hex display for four numbers getting sorted
always @ (posedge clk)
	begin 
	case(outH) 
				4'h0: o1 = 7'b1000000;
				4'h1: o1 = 7'b1111001;
				4'h2: o1 = 7'b0100100;
				4'h3: o1 = 7'b0110000;
				4'h4: o1 = 7'b0011001;
				4'h5: o1 = 7'b0010010;
				4'h6: o1 = 7'b0000010;
				4'h7: o1 = 7'b1111000;
				4'h8: o1 = 7'b0000000;
				4'h9: o1 = 7'b0011000;
				4'hA: o1 = 7'b0001000;
				4'hB: o1 = 7'b0000011;
				4'hC: o1 = 7'b1000110;
				4'hD: o1 = 7'b0100001;
				4'hE: o1 = 7'b0000110;
				4'hF: o1 = 7'b0001110;
		endcase
		
	case(outG) 
				4'h0: o2 = 7'b1000000;
				4'h1: o2 = 7'b1111001;
				4'h2: o2 = 7'b0100100;
				4'h3: o2 = 7'b0110000;
				4'h4: o2 = 7'b0011001;
				4'h5: o2 = 7'b0010010;
				4'h6: o2 = 7'b0000010;
				4'h7: o2 = 7'b1111000;
				4'h8: o2 = 7'b0000000;
				4'h9: o2 = 7'b0011000;
				4'hA: o2 = 7'b0001000;
				4'hB: o2 = 7'b0000011;
				4'hC: o2 = 7'b1000110;
				4'hD: o2 = 7'b0100001;
				4'hE: o2 = 7'b0000110;
				4'hF: o2 = 7'b0001110;
		endcase
	
	case(outF) 
				4'h0: o3 = 7'b1000000;
				4'h1: o3 = 7'b1111001;
				4'h2: o3 = 7'b0100100;
				4'h3: o3 = 7'b0110000;
				4'h4: o3 = 7'b0011001;
				4'h5: o3 = 7'b0010010;
				4'h6: o3 = 7'b0000010;
				4'h7: o3 = 7'b1111000;
				4'h8: o3 = 7'b0000000;
				4'h9: o3 = 7'b0011000;
				4'hA: o3 = 7'b0001000;
				4'hB: o3 = 7'b0000011;
				4'hC: o3 = 7'b1000110;
				4'hD: o3 = 7'b0100001;
				4'hE: o3 = 7'b0000110;
				4'hF: o3 = 7'b0001110;
		endcase
	
	case(outE) 
				4'h0: o4 = 7'b1000000;
				4'h1: o4 = 7'b1111001;
				4'h2: o4 = 7'b0100100;
				4'h3: o4 = 7'b0110000;
				4'h4: o4 = 7'b0011001;
				4'h5: o4 = 7'b0010010;
				4'h6: o4 = 7'b0000010;
				4'h7: o4 = 7'b1111000;
				4'h8: o4 = 7'b0000000;
				4'h9: o4 = 7'b0011000;
				4'hA: o4 = 7'b0001000;
				4'hB: o4 = 7'b0000011;
				4'hC: o4 = 7'b1000110;
				4'hD: o4 = 7'b0100001;
				4'hE: o4 = 7'b0000110;
				4'hF: o4 = 7'b0001110;
			endcase
			
	case(outD) 
				4'h0: o5 = 7'b1000000;
				4'h1: o5 = 7'b1111001;
				4'h2: o5 = 7'b0100100;
				4'h3: o5 = 7'b0110000;
				4'h4: o5 = 7'b0011001;
				4'h5: o5 = 7'b0010010;
				4'h6: o5 = 7'b0000010;
				4'h7: o5 = 7'b1111000;
				4'h8: o5 = 7'b0000000;
				4'h9: o5 = 7'b0011000;
				4'hA: o5 = 7'b0001000;
				4'hB: o5 = 7'b0000011;
				4'hC: o5 = 7'b1000110;
				4'hD: o5 = 7'b0100001;
				4'hE: o5 = 7'b0000110;
				4'hF: o5 = 7'b0001110;			
		endcase
		
	case(outC) 
				4'h0: o6 = 7'b1000000;
				4'h1: o6 = 7'b1111001;
				4'h2: o6 = 7'b0100100;
				4'h3: o6 = 7'b0110000;
				4'h4: o6 = 7'b0011001;
				4'h5: o6 = 7'b0010010;
				4'h6: o6 = 7'b0000010;
				4'h7: o6 = 7'b1111000;
				4'h8: o6 = 7'b0000000;
				4'h9: o6 = 7'b0011000;
				4'hA: o6 = 7'b0001000;
				4'hB: o6 = 7'b0000011;
				4'hC: o6 = 7'b1000110;
				4'hD: o6 = 7'b0100001;
				4'hE: o6 = 7'b0000110;
				4'hF: o6 = 7'b0001110;			
		endcase
		
		case(outB) 
				4'h0: o7 = 7'b1000000;
				4'h1: o7 = 7'b1111001;
				4'h2: o7 = 7'b0100100;
				4'h3: o7 = 7'b0110000;
				4'h4: o7 = 7'b0011001;
				4'h5: o7 = 7'b0010010;
				4'h6: o7 = 7'b0000010;
				4'h7: o7 = 7'b1111000;
				4'h8: o7 = 7'b0000000;
				4'h9: o7 = 7'b0011000;
				4'hA: o7 = 7'b0001000;
				4'hB: o7 = 7'b0000011;
				4'hC: o7 = 7'b1000110;
				4'hD: o7 = 7'b0100001;
				4'hE: o7 = 7'b0000110;
				4'hF: o7 = 7'b0001110;			
		endcase
		
		case(outA) 
				4'h0: o8 = 7'b1000000;
				4'h1: o8 = 7'b1111001;
				4'h2: o8 = 7'b0100100;
				4'h3: o8 = 7'b0110000;
				4'h4: o8 = 7'b0011001;
				4'h5: o8 = 7'b0010010;
				4'h6: o8 = 7'b0000010;
				4'h7: o8 = 7'b1111000;
				4'h8: o8 = 7'b0000000;
				4'h9: o8 = 7'b0011000;
				4'hA: o8 = 7'b0001000;
				4'hB: o8 = 7'b0000011;
				4'hC: o8 = 7'b1000110;
				4'hD: o8 = 7'b0100001;
				4'hE: o8 = 7'b0000110;
				4'hF: o8 = 7'b0001110;			
			endcase	
	end
	
	//hex display for timer
//	always @ (posedge clk) // displays the timer value
//		begin
//			//if (aE == 1'b1)
//			if (count < 6'd10)
//				begin 
//					o6 <= 7'b1000000;
//					case(count) // less than ten
//						6'd0: o5 = 7'b1000000;
//						6'd1: o5 = 7'b1111001;
//						6'd2: o5 = 7'b0100100;
//						6'd3: o5 = 7'b0110000;
//						6'd4: o5 = 7'b0011001;
//						6'd5: o5 = 7'b0010010;
//						6'd6: o5 = 7'b0000010;
//						6'd7: o5 = 7'b1111000;
//						6'd8: o5 = 7'b0000000;
//						6'd9: o5 = 7'b0011000;
//					endcase
//				end
//			else if (count < 6'd20)// greater than or equal to ten
//				begin
//					o6 = 7'b1111001;
//					case(count)
//						6'd10: o5 = 7'b1000000;
//						6'd11: o5 = 7'b1111001;
//						6'd12: o5 = 7'b0100100;
//						6'd13: o5 = 7'b0110000;
//						6'd14: o5 = 7'b0011001;
//						6'd15: o5 = 7'b0010010;
//						6'd16: o5 = 7'b0000010;
//						6'd17: o5 = 7'b1111000;
//						6'd18: o5 = 7'b0000000;
//						6'd19: o5 = 7'b0011000;
//					endcase
//				end
//			else if (count < 6'd30)// greater than or equal to twenty
//				begin
//					o6 = 7'b0100100;
//					case(count)
//						6'd20: o5 = 7'b1000000;
//						6'd21: o5 = 7'b1111001;
//						6'd22: o5 = 7'b0100100;
//						6'd23: o5 = 7'b0110000;
//						6'd24: o5 = 7'b0011001;
//						6'd25: o5 = 7'b0010010;
//						6'd26: o5 = 7'b0000010;
//						6'd27: o5 = 7'b1111000;
//						6'd28: o5 = 7'b0000000;
//						6'd29: o5 = 7'b0011000;
//					endcase
//				end
//			else if (count < 6'd40)// greater than or equal to thirty
//				begin
//					o6 = 7'b0110000;
//					case(count)
//						6'd30: o5 = 7'b1000000;
//						6'd31: o5 = 7'b1111001;
//						6'd32: o5 = 7'b0100100;
//						6'd33: o5 = 7'b0110000;
//						6'd34: o5 = 7'b0011001;
//						6'd35: o5 = 7'b0010010;
//						6'd36: o5 = 7'b0000010;
//						6'd37: o5 = 7'b1111000;
//						6'd38: o5 = 7'b0000000;
//						6'd39: o5 = 7'b0011000;
//					endcase
//				end
//			else if (count < 6'd50)// greater than or equal to fourty
//				begin
//					o6 = 7'b0011001;
//					case(count)
//						6'd40: o5 = 7'b1000000;
//						6'd41: o5 = 7'b1111001;
//						6'd42: o5 = 7'b0100100;
//						6'd43: o5 = 7'b0110000;
//						6'd44: o5 = 7'b0011001;
//						6'd45: o5 = 7'b0010010;
//						6'd46: o5 = 7'b0000010;
//						6'd47: o5 = 7'b1111000;
//						6'd48: o5 = 7'b0000000;
//						6'd49: o5 = 7'b0011000;
//					endcase
//				end
//			else if (count < 6'd60)// greater than or equal to fifty
//				begin
//					o6 = 7'b0010010;
//					case(count)
//						6'd50: o5 = 7'b1000000;
//						6'd51: o5 = 7'b1111001;
//						6'd52: o5 = 7'b0100100;
//						6'd53: o5 = 7'b0110000;
//						6'd54: o5 = 7'b0011001;
//						6'd55: o5 = 7'b0010010;
//						6'd56: o5 = 7'b0000010;
//						6'd57: o5 = 7'b1111000;
//						6'd58: o5 = 7'b0000000;
//						6'd59: o5 = 7'b0011000;
//					endcase
//				end
//			else                //greater then or equal to sixty
//				begin
//					o6 = 7'b0000010;
//					case (count)
//						6'd60: o5 = 7'b1000000;
//						6'd61: o5 = 7'b1111001;
//						6'd62: o5 = 7'b0100100;
//						6'd63: o5 = 7'b0110000;
//					endcase
//				end
//		end
	endmodule
	